This invention relates principally to the surface mount solder assembly of leadless integrated circuit packages to a substrate and particularly to a process for controlling a geometry of a solder joint.
A major problem in the solder assembly of leadless integrated circuit packages to a substrate is the reliability of the solder joints. These solder joints are commonly subjected to severe thermo-mechanically induced stresses and strains principally due to the unequal thermal expansion of the integrated circuit package and the substrate. The large temperature excursions which tend to occur regularly over the life of electronic systems give rise to moderately large cyclic plastic strains in the solder joints which in turn may result in low cyclic fatigue failures in the joints. In addition, flexing of the substrate relative to the integrated circuit package may induce additional stresses and strains in the solder joints.
Another problem is the tendency of solder joints to fail to form properly during the soldering process. The solder may fail to properly wet the terminal pads or lands of the integrated circuit package or substrate and thereby produce a mechanically and electrically unsound solder joint, or adjacent joints may bridge, thereby, interconnecting two terminals that are otherwise to be electrically isolated from one another. The large package size and high density of interconnections of high lead count VLSI chip packages significantly aggravates the problem of producing assuredly reliable solder joints.
The various thermo-mechanically induced stresses and strains occur both within the solder joint and at the solder to package or solder to substrate interface. It has been found that considerable improvement in reliability may be achieved by producing elongated solder joints with a well controlled shape or geometry as opposed to accepting an amorphous or poorly controlled geometry or shape of the traditional lap solder joint.
While the implementation of the traditional lap solder joint is relatively simple, the increase in lead count of integrated circuit packages and the many problems enumerated above dictate that shaping techniques and alternative constructions be used in creating solder joints. Existing shaping techniques include solder bumping and casting tin pillars.
In solder bumping, solder preforms generally in the form of spheres, are initially bonded to the integrated circuit package terminal pads or lands. This package with its solder bumps is then placed over corresponding lands on the substrate and the solder is reflowed to form the electrical connection between the package and the substrate. Since the shape of the solder joint is primarily controlled by surface tension and package weight, the resulting shape of the solder joint has a truncated spherical geometry. The truncated spherical solder joint shape creates an acute angle at its junction with the land to which it is bonded. This angular junction is a source of high stress concentration at the interface between the solder joint and the pad to which it is bonded. The truncated spherical solder joint also has a poor strain distribution along the joint height, concentrating the plastic strain in low cross sectional areas near the aforementioned interfaces with the terminal pads. Consequently such joints are quite susceptible to low cycle fatigue failures. It is further apparent that the truncated spherical shape characteristic of solder bumping is undersirable for high lead densities since tall joints may not be produced without also producing wide joints and closely spaced solder joints may tend to bridge with one another.
An improvement over the conventional bumped solder joint is the cast tin pillar joint. In this approach, a tin pillar is first cast onto each of the terminal pads of the integrated circuit package. Solder paste is deposited onto the lands of the substrate and the package with its cast pillars is then placed over the corresponding lands of the substrate and reflow soldered to form a butt joint between the cast tin pillar and the associated substrate land. The combined cast tin pillar and solder butt joint together form a somewhat hourglass shaped joint. This shape significantly reduces the stress induced in the cast pillar to terminal pad interface and the solder joint to land interface and thereby increases the joint reliability. Taller joints may be produced with this technique so that the strain levels are reduced and the strains are more favorably distributed throughout the volume of the joint as compared with joints formed with conventional solder bumping techniques. The resulting joint shape is thus more forgiving of differential temperature expansion of substrate and package in terms of stress induced in the joint.
A solder bumping technique is disclosed by P. M. Hall et al., in U.S. Pat. No. 4,352,449, issued October 5, 1982. Preforms or solder spheres are applied to the terminal pads of the integrated circuit package and reflowed to form solder bumps on the package. This package with its solder bumps is then placed over corresponding lands on the substrate and the solder is reflowed to form an electrical connection between the package and the substrate. During reflow the weight of the package is supported by the molten solder joints which are contained by surface tension. By careful selection of the size of the applied solder spherical preforms, based on an engineering analysis, the final separation between the package and substrate can be well controlled. This method, however, does not permit the desired degree of control over the final shape or geometry of the solder joint.
A solder assembly technique using cast solder leads with pillar shapes is disclosed in U.S. Pat. No. 4,412,642 issued to J. R. Fisher on November 1, 1983. This technique utilizes a mold with shaped cavities to cast shaped tin pillars onto the pads of the package. Solder paste is deposited onto the lands of the substrate and the package with its cast pillars is then placed over the corresponding lands and reflow soldered to form a butt joint between the cast tin pillar and the associated substrate pad. The final separation between the package and the substrate is dependent on the height of the cast tin pillars and dependent on the degree to which these pillars are shortened by dissolution into the molten solder formed by the paste during the solder reflow assembly operation.
Another solder assembly method for forming circuit interconnections between adjacent circuit layers of a multilayer circuit structure is disclosed in U.S. Pat. No. 3,835,531, issued to W. Luttmer on Sept. 17, 1974. A pattern of conductive solder bumps or protrusions is formed on each layer with protrusions on one substrate aligned with protrusions on another substrate. An insulation layer of heat curable material is placed between the two substrates and the substrates are brought together so that the protrusions pierce the intervening insulation layer and corresponding protrusions contact one another. The intervening layer which is now contiguous to both substrates is heated and cured to form an adhesive bond. Finally the solder protrusions are fused to form a solder joint. To perform this process, an insulative layer must be provided which is readily pierced by dull solder protrusions such that they touch and can be reflowed together. Thus, nonuniformity of protrusion height or warpage of the substrates creates a possibility of noncontact, and hence uncertainty of making the desired connection. The resultant assembly is furthermore bonded together and not readily disassembled.
Yet another method of solder assembly is disclosed in U.S. Pat. No. 3,827,918, issued to T. J. Ameen et al., on August 6, 1974. The technique disclosed therein uses chromate conversion coatings adjacent to the lands as a barrier to prevent wicking of molten solder. Assembly is by deposition of solder mounds on the land areas on the substrate and circuit device followed by reflowing to melt the solder. This method does not permit the desired control over the solder joint shape or geometry.
Another solder assembly technique known as controlled collapse is disclosed in an article entitled, "Controlled Collapse Reflow Chip Jointing" by L. F. Miller in theIBM Journal of Research and Development of May, 1969. The collapse of solder deposits during reflow soldering is limited by limiting the solderable area of substrate lands and chip contact terminals to permit surface tension to support the chip device and maintain separation until the solder solidifies. In certain applications, solder is placed on a chip pad where no corresponding substrate pad exists so that the surface tension of this molten solder will operate solely to maintain a desired separation. This technique, again does not provide an adequate means of controlling the geometry of the resultant solder joints.
Another soldering method is disclosed by R. Kimeto et al., in an article entitled, "The Soldering Of Microchip Carriers For PCB" in the International Journal For Hybrid Microelectronics; Vol. 5, No. 2, November 1982, pp. 296-299, in which a solder bump is formed on an integrated circuit package and a solder pedestal is formed on the printed circuit board. The melting point of the solder bumps is higher than that of the solder pedestals. The solder bumps and solder pedestals are aligned with one another and heated to preconnect them and deform them so that height irregularities of bumps and pedestals are absorbed. When all terminals are in firm contact, the assembly is heated at a temperature between the two distinct melting points of the bumps and pedestals to form the final solder connection. No provision is made, however, to control the resultant solder joint geometry.
A variant of controlled collapse known as a self-stretching technique has been disclosed by Ryohey Satoh et al., in an article entitled "Development of a New Micro-Solder Bonding Method for VLSI" in Conference Proceedings For The Third Annual International Electronics Packaging Conference, Itasca, Illinois, dated October 24, 25 and 26, 1983. In this method, a controlled amount of solder having a given melting point is deposited on the pad areas of an integrated circuit package which are to be soldered to corresponding pad areas on a substrate. A second controlled volume of solder having a higher melting point is deposited as a sheet over and extending beyond a pad area on the substrate in an area in which there is no corresponding wettable surface on the chip package. Upon heating the joint, the low temperature solder melts first and makes the electrical connection. The control sheet melts subsequently and forms a quasi-spherical shape whose surface tension generates forces that move the chip and substrate away from each other to a desired distance.
This method does theoretically provide a means of controlling solder joint shape by using surface tension of the control sheet to support the package at a distance from the substrate in order to achieve a more reliable older joint geometry. However, the control of joint geometry and alignment of chip carrier and substrate is difficult to control precisely with this method, due to possible variations in process parameters such as surface tension of the solder as it is influenced by fluxing.